// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_nvme_pf_local_ctrl_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_H__
#define __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_H__

/* HIPCIEC_NVME_PF_LOCAL_CTRL_REG Base address of Module's Register */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE                       (0x80200)

/******************************************************************************/
/*                      HiPCIECTRL40V200 HIPCIEC_NVME_PF_LOCAL_CTRL_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_CAP_LOW_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x0)  /* NVMe Controller Capabilities Low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_CAP_HIGH_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x4)  /* NVMe Controller Capabilities High */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_VS_REG        (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x8)  /* NVMe Controller Version */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_INTMS_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0xC)  /* NVMe Controller Interrupt Mask */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_INTMC_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x10) /* NVMe Controller Interrupt Clear */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_CONFIG_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x14) /* NVMe Controller Configuration */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_CTRL_STATUS_REG    (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x1C) /* NVMe Controller Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_NVME_SUBSYS_RST_REG     (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x20) /* NVMe subsystem Reset */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_AQA_REG                 (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x24) /* NVMe Admin Queue Attributes */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_LOW_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x28) /* NVMe Admin Submission Queue Base Addrss low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ASQB_HIGH_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x2C) /* NVMe Admin Submission Queue Base Addrss high */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_LOW_REG            (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x30) /* NVMe Admin Completion Queue Base Address low */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_ACQB_HIGH_REG           (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x34) /* NVMe Admin Completion Queue Base Address high */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CMBLOC_REG              (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x38) /* NVMe Controller Memory Buffer Location */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_CMBSZ_REG               (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x3C) /* NVMe Controller Memory Buffer Size */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CTRL_REG_INT_STS_REG (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x40) /* Write Controller Register Interrupt Status */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_SQ_DB_INT_STS0_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x44) /* Write SQ doorbellinterrupt status0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_SQ_DB_INT_STS1_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x48) /* Write SQ doorbellinterrupt status1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_SQ_DB_INT_STS2_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x4C) /* Write SQ doorbellinterrupt status2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_SQ_DB_INT_STS3_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x50) /* Write SQ doorbellinterrupt status3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_STS0_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x54) /* Write CQ doorbellinterrupt status0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_STS1_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x58) /* Write CQ doorbellinterrupt status1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_STS2_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x5C) /* Write CQ doorbellinterrupt status2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_STS3_REG   (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x60) /* Write CQ doorbellinterrupt status3 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_INT_REQ_REG             (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x70) /* Write Local Int to Host */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_MASK0_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x74) /* Write CQ doorbell interrupt mask0 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_MASK1_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x78) /* Write CQ doorbell interrupt mask1 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_MASK2_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x7C) /* Write CQ doorbell interrupt mask2 */
#define HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_WR_CQ_DB_INT_MASK3_REG  (HiPCIECTRL40V200_HIPCIEC_NVME_PF_LOCAL_CTRL_REG_BASE + 0x80) /* Write CQ doorbell interrupt mask3 */

#endif // __HIPCIEC_NVME_PF_LOCAL_CTRL_REG_REG_OFFSET_H__
